[视频作者] 屏幕反弹
[视频时长] 616:57
[视频类型] 野生技术协会
https://www.eecourse.com/course/211 学完课程收获 1、Simulate Verilog/SystemVerilog designs using VCS. 2、Debug Verilog/SystemVerilog designs using VCS. 3、Run fast RTL-Level regression test for your designs. 4、Run fast Gate-Level regression test for your desig